A conventional liquid crystal display device includes a controller 1001, a source driver 1002, a gate driver 1003, and a liquid crystal panel 1004, as shown in FIG. 9. The liquid crystal panel 1004 described herein uses TFTs (Thin Film Transistors) as the switching element.
The source driver 1002 produces a gray level display signal C based on signal A that is sent from the controller 1001, so as to drive source signal lines of the liquid crystal panel 1004. Examples of signal A includes: serially transferred digital display data A3; a start pulse signal A1 for the source driver, which initiates importing of the display data A3; and a latch signal A2 that latches display data of one horizontal synchronous period, as shown in FIG. 10.
The source driver 1002 operates as follows. In response to a transfer clock signal CKs, the serially transferred display data A3 for image display is held with respect to each output terminal. Based on the display data A3, the gray level display signal C is generated and supplied to each pixel of the liquid crystal panel 1004, so as to decide the brightness of each pixel.
The gate driver 1003 is used to drive each gate signal line of the TFT liquid crystal panel 1004. Specifically, the gate driver 1003 receives a signal B and a transfer clock signal CKg, the signal B being a first line display start signal (start pulse signal for the gate driver), for example. In response to the input of these signals, the gate driver 1003 produces a scanning signal D that sequentially selects display lines, and outputs the scanning signal D to each gate signal line.
The gray level display signal C from the source driver 1002 and the scanning signal D, used to sequentially select display lines, from the gate driver 1003 are so used by the liquid crystal display device to display gray levels (multi-color display) per each gate signal line on the display screen of the liquid crystal panel 1004.
The source driver 1002 is described below in more detail with reference to the block diagram of FIG. 10. The source driver 1002 includes a shift register 1005, a latch memory 1006, a hold memory 1007, a gray level voltage selector 1008, and a gray level voltage generator 1009.
The shift register 1005 starts being operated by the start pulse A1 that initiates drawing data, and outputs a signal F1 in synchronism with the transfer clock signal CKs. The latch memory 1006 draws the serially transferred display data A3 in response to the start pulse signal F1.
The latch memory 1006 is set for each output of the source signal lines. The latch memory 1006 of each output is sequentially selected by the start pulse signal F1, so that the serially transferred display data A3 is sequentially stored in the latch memory of each output. As a result, the serially transferred display data A3 is converted into parallel display data in the source driver 1002.
The display data A3 stored in the latch memory 1006 is transferred to the hold memory 1007 (F2) and is latched by the latch signal A2 corresponding to one horizontal synchronizing signal.
The display data so transferred is sent to the gray level voltage selector 1008 (F3). The gray level voltage selector 1008 selects a gray level display voltage E_x according to the display data from a plurality of gray level display voltages E generated in the gray level voltage generator 1009.
The hold memory 1007 is required to compensate for a delay in charging a pixel capacitance or signal line capacitance of the liquid crystal panel 1004 to bring their potentials to the level of the selected gray level display voltage E_x. The hold memory 1007 stores the display data A3 for one horizontal synchronous period, so as to permit the display data A3 of the next line to be stored in the latch memory 1006 while charging the pixel capacitance or signal line capacitance of the liquid crystal panel 1004.
Referring to FIG. 11, the following describes the gray level voltage generator 1009. The gray level voltage generator 1009 includes a plurality of serially connected resistors R, and a plurality of operational amplifiers 1015 whose non-inverted terminals are connected to each junction between the resistors R and at the both ends of the resistors R. The number of resistors R and the number of operational amplifiers 1015 are set according to the number of gray levels. The output signal from the output terminal of the operational amplifier 1015 is connected to the inverted terminal to create a feedback loop, so that the operational amplifier 1015 serves as a voltage follower that presents a low output impedance.
In the gray level voltage generator 1009, the intermediate voltage of the externally supplied voltages VinpH and VinpL from the both ends of the resistors R is divided by the resistors R. Each fraction of the voltage so divided is subjected to impedance conversion by the operational amplifiers 1015, so as to output the resulting voltages (signals E_1 through E_n) to the gray level voltage selector 1008.
As shown in FIG. 12, the gray level voltage selector 1008 is provided for each output terminal of the hold memory 1007. According to the display data stored in the hold memory 1007, the gray level voltage selector 1008 selects one of the gray level display voltages E_1 through E_n generated in the gray level voltage generator 1009, and outputs a gray level display signal C_x for driving the liquid crystal panel 1004.
As shown in FIG. 13, in the gray level voltage selector 1008, the display data F3, which has been produced by holding the display data A3 in parallel, is received by the multiplexer 1012. The multiplexer 1012 produces a signal G3_x that selects and closes one of the switches 1011 respectively corresponding to the gray level display voltages.
The switch 1011 is, for example, an analog switch that is realized by a pair of PchMOS transistor 1013 and NchMOS transistor 1014, and an inverter 1016 that inverts an input signal to the gate of the NchMOS transistor 1014 so as to supply it to the gate of the PchMOS transistor 1013 (see FIG. 14). Selecting the switch 1011 enables a gray level display voltage to be selected according to the display data F3 and outputted as the gray level display signal C.
In this manner, the LSI, i.e., the source driver 1002, that supplies the gray level display signal C to the liquid crystal display device generates a voltage for each of the gray levels when displaying gray levels according to the video signal, i.e., the display data A3. This is achieved by externally supplying part of gray level display voltages (e.g., a maximum voltage VinpH and a minimum voltage VinpL) to the source driver 1002 and producing therein intermediate voltages. The gray level voltage selector 1008 selects a voltage according to the gray level with respect to each output terminal.
Further, as described above, the liquid crystal panel 1004 has a capacitive load, which causes a voltage drop during charging or discharging of the panel capacitance. In order to prevent this, a buffer circuit such as the operational amplifier 1015 needs to be provided between the terminal of each gray level display voltage and the output terminal, so as to present a low output impedance.
Unlike a digital signal, the voltage levels of the gray level display voltages are highly accurate, and they do not tolerate voltage fluctuations between input and output of the buffer circuit. It is therefore conventionally common that the buffer circuit uses the operational amplifier 1015, which is an analog circuit, as a voltage follower.
One problem of the operational amplifier 1015, however, is that it generally consumes large power. Thus, the power consumption of the source driver 1002 is increased as a whole when the number of gray level display voltages is increased to improve image quality, because in this case the number of operational amplifiers 1015 is increased.
Further, because the gray level display voltages have the same chance of being used, the operational amplifier 1015, which is provided for each gray level display voltage, needs to be operated at all times. This poses the problem of power consumption.
For example, when the source driver 1002 is to display 64 gray levels, 64 operational amplifiers 1015 need to be operated at all times. Similarly, displaying 256 gray levels requires 256 operational amplifiers 1015. That is, increasing the number of gray levels increases the consumed current and thereby increases power consumption.